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make is a utility that automatically builds files, which are often executable, or libraries from basic elements such as source code. Generally it is used to automatize compiling and linking programs.

The make command interprets and executes the instructions within a file named makefile, that specifies how to build key files. As opposed to a simple script, make only executes the commands that are necessary. The goal is to arrive at a result (compiled or installed software, created documentation, etc.) without needing to redo all steps.

In the makefile you can find information on dependencies. For example, if an executable depends on object files, and if some of those have changed, rebuilding the program is necessary. In the same way, object files depend on their associated source files, and if a source file has been modified, it must be recompiled to recreate the new object file. All dependencies must be included in the makefile. Then it is no longer necessary to recompile all files for every modification, the make command takes care of recompiling and relinking only what is necessary. It is also possible to use environment and internal variables inside a makefile.

Examples for using make

The main argument of the make command is usually the target. This is the component that make must build. The targets that are available depend on the contents of the makefile, but some targets are very common. Those common targets are all, test, check, clean, and install. If no target is specified, that is by using

[name@server $] make

typical behaviour is to construct everything, equivalent to

[name@server $] make all

The test or check targets are generally used to run tests to validate if the application or compiled library functions correctly. Usually these targets depend on the all target. Hence you can verify the compilation using

[name@server $] make all && make check


[name@server $] make all && make test

The clean keyword erases all previously compiled binary files to be able to recompile from scratch. There is sometimes also a distclean target, which not only deletes files made by make, but also files created at configuration time by configure or cmake. So to clean the compilation directory, you can usually run

[name@server $] make clean

and sometimes

[name@server $] make distclean

The install target normally installs a compiled program or library. Where the installation is put depends on the makefile, but can often be modified using an additional prefix parameter, like thisL

[name@server $] make install prefix=$HOME/PROGRAM

The above targets are only conventions and a makefile author could very well choose another convention. To get more information on typical target names, notably supported by all GNU applications, visit this page. Options to configure installation and other directories are listed here.

Example of a Makefile

The following example, of general use, includes a lot of explanations and comments. For a detailed guide on how to create a makefile, visit the GNU Make web site.

File : Makefile
# Makefile to easily update the compilation of a program (.out)
# --------
# by Alain Veilleux, 4 August 1993
#    Last revision : 30 March 1998
#    Script in the form of a "Makefile" allowing to update a program containing
#    multiple seperated routines on the disk. This script is not executed by itself,
#    but is instead read and interpreted by the "make" command. When it is called,
#    the "make" command verifies the dates of the various components your program is
#    build from. Only routines that were modified after the last compilation of the
#    program are recompiled in object form (files ending in .o). Recompiled .o files
#    are subsequently linked together to form an updated version of the final program.
#    Modify the contents of the variables hereunder. Comments will guide you how and
#    where.
#    1- Type "make" to update the whole program.
#    2- Type "make RoutineName" to only update the RoutineName routine.
#====================  Definition of variables  =====================
# Remark : variables are sometimes called "macros" in Makefiles.
# Compiler to use (FORTRAN, C or other)
CompilerName= xlf
# Compilation options: the below options are usually used to compile FORTRAN
#                      code. You can assign other values than those suggested
#                      in the "CompilationOptions" variables.
#CompilationOptions= -O3
# Remove the below "#" to activate compilation in debug mode
#CompilationOptions= -g
# Remove the below "#" to use "gprof", which indicates the computation time in
#    each subroutine
#CompilationOptions= -O3 -pg
# List of routines to compile: here we list all object files that are needed.
# Put a "\" at the end of each line that if you want to continue the list of
#    routines on the following line.
ObjectFiles= trnb3-1.part.o mac4251.o inith.o dsite.o initv.o main.o \
             entree.o gcals.o defvar1.o defvar2.o magst.o mesure.o
# Name of the final executable
ProgramOut= trnb3-1.out
#=====  End of variable definitions =====
#===============  There is nothing to change starting here  =============
# Defines a rule: how to build an object file (ending in ".o")
#                 from a source file (ending in ".f")
# note: "$<" symbols will be replaced by the name of the file that is compiled
# Compiling Fortran files:
	$(CompilerName) $(CompilationOptions) -c $<
# Defines a rule: how to build an object file (ending in ".o")
#                from a source file (ending in ".c")
# note: "$<" symbols will be replaced by the name of the file that is compiled
# Compiling C files:
$(CompilerName) $(CompilationOptions) -c $<
# Defines a rule: how to build an object file (ending in ".o")
#                 from a source file (ending in ".C")
# note: "$<" symbols will be replaced by the name of the file that is compiled
# Compiling C++ files:
	$(CompilerName) $(CompilationOptions) -c $<
# Dependencies of the main executable on the object files (".o") it is built from.
# The dependency of object files on source files (".f" and ".c") is implied by the above
# implicit rules.
$(ProgramOut): $(ObjectFiles)
	$(CompilerName) $(CompilationOptions) -o $(ProgramOut) \

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